The present invention relates to a polyphase signal generator which generates signals spaced in phase 90 degrees apart. In particular, this invention relates to a polyphase signal generator which implements the equivalent function with a small-scale circuit configuration.
A conventional four-phase signal generator will be taken as an example of a conventional polyphase signal generator. FIG. 2 shows a configuration of a conventional four-phase signal generator which is explained in C-12-11, 2001 National Convention Record of the Institute of Electronics, Information and Communication Engineers of Japan.
In FIG. 2, reference number 1 denotes a first signal input terminal, 2 denotes a second signal input terminal, 3 denotes a first signal output terminal, 4 denotes a second signal output terminal, 11 denotes a first delay circuit, 12 denotes a second delay circuit, 21 denotes a first phase interpolation circuit, 22 denotes a second phase interpolation circuit, 211 denotes a third signal input terminal, 212 denotes a fourth signal input terminal, 221 denotes a fifth signal input terminal, and 222 denotes a sixth signal input terminal.
Operation of the conventional four-phase signal generator will now be explained. The first delay circuit 11 and the second delay circuit 12 have the same configuration and provide equal phase delays xcex8. The first phase interpolation circuit 21 and the second phase interpolation circuit 22 have the same configuration and equal internal phase delays xcex4. A signal phase of the third signal input terminal 211 is denoted by IN21a. A signal phase of the fourth signal input terminal 212 is denoted by IN21b. A signal phase of the fifth signal input terminal 221 is denoted by IN22a. A signal phase of the sixth signal input terminal 222 is denoted by IN22b. An output signal phase of the first signal output terminal 3 is denoted by OUT0, and an output signal phase of the second signal output terminal is denoted by OUT90.
Signals spaced in phase 180 degrees apart are input to the first signal input terminal 1 and the second signal input terminal 2. The phase shift of 180 degrees can be obtained easily by inverting a signal. Denoting a signal phase of the first signal input terminal 1 by IN0 and a signal phase of the second signal input terminal 2 by IN180, therefore, the following equations are satisfied as regards signal phases.
xe2x80x83INO=0xe2x80x83xe2x80x83(1)
INI180=180xe2x80x83xe2x80x83(2)
An output of the first delay circuit 11 is connected to both the third signal input terminal 211 and the fourth signal input terminal 212. As regards the phases, therefore, the following equation is satisfied.
IN21a=IN21b=IN0+xcex8=xcex8xe2x80x83xe2x80x83(3)
An output of the second delay circuit 12 is connected to the fifth signal input terminal 221. The second signal input terminal 2 is connected to the sixth signal input terminal 222. Therefore, the following equations are satisfied as regards signal phases.
IN22a=IN0+2xc2x7xcex8=2xc2x7xcex8xe2x80x83xe2x80x83(4)
IN22b=INI180=180xe2x80x83xe2x80x83(5)
The first phase interpolation circuit 21 and the second phase interpolation circuit 22 output signals with output phases represented by the following equations in response to two signal input phases.                                                         OUT0              =                              xe2x80x83                            ⁢                              δ                +                                                      (                                          IN21a                      +                      IN21b                                        )                                    /                  2                                                                                                        =                              xe2x80x83                            ⁢                              δ                +                θ                                                                        (        6        )                                                                    OUT90              =                              xe2x80x83                            ⁢                              δ                +                                                      (                                          IN22a                      +                      IN22b                                        )                                    /                  2                                                                                                        =                              xe2x80x83                            ⁢                              δ                +                                                      (                                                                  2                        ·                        θ                                            +                      180                                        )                                    /                  2                                                                                                        =                              xe2x80x83                            ⁢                              δ                +                θ                +                90                                                                        (        7        )            
It will be appreciated from the equations (6) and (7) that the signal phase of the first signal output terminal 3 and the signal phase of the second signal output terminal 4 always maintain the phase difference relation of 90 degrees irrespective of the phase delay xcex8 of the first delay circuit 11 and the second delay circuit 12 and the internal phase delay xcex4 of the first phase interpolation circuit 21 and the second phase interpolation circuit 22. In other words, even when the phase delays xcex8 and xcex4 are varied by a variation of an environment such as the operation temperature or the power supply voltage, four-phase signals spaced in phase accurately 90 degrees apart can be obtained from the output signal of the first signal output terminal 3, the output signal of the second signal output terminal 4, an inverted output signal of the first signal output terminal 3, and an inverted output signal of the second signal output terminal 4.
Operation of the phase interpolation circuits will now be explained. FIG. 3 is a diagram showing an example of a detailed configuration of the first phase interpolation circuit 21 and the second phase interpolation circuit 22. In FIG. 3, reference number 51 denotes a high potential power supply voltage, 52 denotes a low potential power supply voltage, 53 denotes a first positive-phase input terminal, 54 denotes a first negative-phase input terminal, 55 denotes a second positive-phase input terminal, 56 denotes a second negative-phase input terminal, 57 denotes a positive-phase output terminal, 58 denotes a negative-phase output terminal, 59 denotes a first current source, 60 denotes a second current source, 61-64 denote NPN transistors, and 65 and 66 denote resistors. The first signal output terminal 3 and the second signal output terminal 4 shown in FIG. 1 correspond to the positive-phase output terminal 57 and the negative-phase output terminal 58 shown in FIG. 3.
The first current source 59 and the second current source 60 flow currents of the same current value I0. The NPN transistors 61 to 64 have the same characteristic. The resistor 65 and the resistor 66 have the same resistance value R. The first positive-phase input terminal 53 is the third signal input terminal 211 shown in FIG. 2. The second positive-phase input terminal 55 is the fourth signal input terminal 212 shown in FIG. 2. Each of the first negative-phase input terminal 54 and the second negative-phase input terminal 56 is supplied with a reference voltage.
Supposing an input signal IN21a of the first positive-phase input terminal 53 and an input signal IN21b of the second positive-phase input terminal 55 to be sine waveforms, t to be time, xcfx86(t) to be a phase at the time t, "xgr" to be a phase difference between IN21a and IN21b, and Vref to be the reference voltage applied to the first negative-phase input terminal 54 and the second negative-phase input terminal 56, the input signal IN21a and the input signal IN21b can be represented by the following equations.
IN2la=Vref+sin xcfx86(t)xe2x80x83xe2x80x83(8)
IN21b=Vref+sin{xcfx86(t)+xcex6}(9)
If each of a differential pair formed of the NPN transistors 61 and 62 and a differential pair formed of the NPN transistors 63 and 64 conducts a linear operation in response to its input signal, it divides a current source current I0 in proportion to an amplitude of the input signal. Supposing a high potential power supply voltage 51 to be Vcc, therefore, a collector current Ia1 of the NPN transistor 61, a collector current Ib1 of the NPN transistor 63, and an output voltage V2 of the negative-phase output terminal 58 can be represented by the following equations.                     Ia1        =                              (                          I0              /              2                        )                    ⁢                      xe2x80x83                    ⁢                      {                          1              +                              sin                ⁢                                  xe2x80x83                                ⁢                ϕ                ⁢                                  xe2x80x83                                ⁢                                  (                  t                  )                                                      }                                              (        10        )                                Ib1        =                              (                          I0              /              2                        )                    ⁢                      xe2x80x83                    [                      1            +                          sin              ⁢                              xe2x80x83                            ⁢                              {                ϕ                }                            ⁢                              xe2x80x83                            ⁢                              (                t                )                                      +            ζ                    ]                                    (        11        )                                                                    V2              =                              xe2x80x83                            ⁢                              Vcc                -                                  R                  ⁢                                      {                                          Ia1                      +                      Ia2                                        }                                                                                                                          =                              xe2x80x83                            ⁢                              Vcc                -                                                      R                    ⁡                                          (                                              I0                        /                        2                                            )                                                        ⁢                                      xe2x80x83                                    [                                      2                    +                                          sin                      ⁢                                              xe2x80x83                                            ⁢                      ϕ                      ⁢                                              xe2x80x83                                            ⁢                                              (                        t                        )                                                              +                                          sin                      ⁢                                              xe2x80x83                                            ⁢                                              {                                                                              ϕ                            ⁢                                                          xe2x80x83                                                        ⁢                                                          (                              t                              )                                                                                +                          ζ                                                }                                                                              ]                                                                                                        =                              xe2x80x83                            ⁢                              Vcc                -                                                      R                    ⁡                                          (                                              I0                        /                        2                                            )                                                        ⁢                                      xe2x80x83                                    [                                      2                    +                                          2                      xc3x97                      cos                      ⁢                                              xe2x80x83                                            ⁢                                              (                                                  ζ                          /                          2                                                )                                            xc3x97                      sin                      ⁢                                              xe2x80x83                                            ⁢                                              {                                                                              ϕ                            ⁢                                                          xe2x80x83                                                        ⁢                                                          (                              t                              )                                                                                +                                                      ζ                            /                            2                                                                          }                                                                              ]                                                                                                        =                              xe2x80x83                            ⁢                              Vcc                -                                  R                  xc3x97                                      I0                    ⁢                                          xe2x80x83                                        [                                          1                      +                                              cos                        ⁢                                                  xe2x80x83                                                ⁢                                                  (                                                      ζ                            /                            2                                                    )                                                xc3x97                        sin                        ⁢                                                  xe2x80x83                                                ⁢                                                  {                                                                                    ϕ                              ⁢                                                              xe2x80x83                                                            ⁢                                                              (                                t                                )                                                                                      +                                                          ζ                              /                              2                                                                                }                                                                                      ]                                                                                                                          =                              xe2x80x83                            ⁢                              Vbias                -                                  Vpp                  xc3x97                  sin                  ⁢                                      xe2x80x83                                    ⁢                                      {                                                                  ϕ                        ⁢                                                  xe2x80x83                                                ⁢                                                  (                          t                          )                                                                    +                                              ζ                        /                        2                                                              }                                                                                                          (        12        )            
In the equations, Vbias is a bias voltage of an output signal, and Vpp is a maximum amplitude of the output signal. They can be represented by the following equations.
Vbias=Vccxe2x88x92Rxc3x97I0xe2x80x83xe2x80x83(13)
Vpp=Rxc3x97I0xc3x97cos{xcex6/2}xe2x80x83xe2x80x83(14)
An output voltage V1 of the positive-phase output terminal 57 can be represented by the following equation as a result of derivation similar to that in the foregoing explanation.
V1=Vbias+Vppxc3x97sin{xcfx86(t)+xcex6/2}xe2x80x83xe2x80x83(15)
Thus, in each phase interpolation circuit, the phase of the output signal becomes "xgr"/2 in response to the two input signals having the phase difference "xgr", as represented by the equations (12) and (15). If, for example, the internal phase delay 8 is added, therefore, the equation (6) and the equation (7) regarding the phases are satisfied.
In the conventional polyphase signal generator, the signals spaced in phase 90 degrees apart are generated by using the two delay circuits 11 and 12 and the two phase interpolation circuits 21 and 22 as described above. Thus, there is a room for improvement in reduction of the size of the circuit and power dissipation.
It is an object of the present invention to obtain a polyphase signal generator in which the similar function can be implemented by using a circuit configuration which is smaller in scale as compared with the conventional configuration. Moreover, it is another object of this invention to achieve reduction of the power dissipation.
The polyphase signal generator according to the present invention comprises a signal receiving terminal which receives an input signal, a delay addition unit which adds a desired phase delay to the received input signal. Moreover, there is provided a first output signal generation unit having two input terminals. The first output signal generation unit receives the input signal through one of the input terminals and receives the phase delayed signal output from the delay addition unit through the other input terminal. The first output signal generation unit generates a first output signal based on a phase difference between the received input signal and the phase delayed signal. In addition, there is provided a signal inverting unit which receives and inverts the input signal. Furthermore, there is provided a second output signal generation unit having two input terminals. The second output signal generation unit receives the inverted input signal output from the signal inverting unit through one of the input terminals and receives the phase delayed signal output from the delay addition unit through the other input terminal. The second output signal generation unit generates a second output signal based on a phase difference between the received inverted input signal and the phase delayed signal.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.